Compute & Infrastructure

Microsoft has disclosed a plan to reach 38 gigawatts of total data centre capacity, with the incremental 26 gigawatts representing new AI-focused build, according to Bloomberg. Critically, the reporting confirms that shortfalls in existing capacity have already resulted in Microsoft turning away AI and cloud business — this is not a forward-looking demand signal but a confirmed, revenue-impacting constraint that has already materialised. The 38GW target is an announced plan, not committed capacity; the pace at which this translates to operational infrastructure depends on grid interconnection queues, permitting timelines, and hardware procurement.

Oracle's parallel data point reinforces the demand picture: cloud sales more than doubled and beat analyst estimates, with the company attributing outperformance directly to AI data centre investment paying off, per Bloomberg. Together, these two disclosures indicate that the capacity constraint is broad-based across hyperscalers, not idiosyncratic to Microsoft. The supply-demand gap is now sufficiently large that it is showing up in missed revenue, which is a more durable forcing function for capital deployment than forward projections alone.

Biren Technology reported 2,000% year-over-year revenue growth in the first half of 2026, according to Tom's Hardware. The company is the direct beneficiary of the vacuum created by successive rounds of US export restrictions that have pushed NVIDIA and AMD out of the Chinese AI accelerator market. This is a confirmed shipment and revenue figure from H1 2026, not an analyst projection, and the magnitude is significant enough to represent a structural shift rather than a one-time inventory draw.

The strategic read here is that export controls are functioning as intended from a US policy standpoint — NVIDIA and AMD are absent from the Chinese market — but the second-order effect is the accelerated maturation of domestic Chinese silicon. Biren, alongside Cambricon and Huawei's Ascend line, is now operating in a protected domestic market with guaranteed demand and no Western competition. The long-run risk is not that China matches leading-edge performance immediately, but that it builds the production scale, supply chain integration, and software ecosystem to close the gap faster than external pressure alone would have forced.

Ajinomoto Build-up Film substrates — the interconnect layer between chip and PCB in every advanced AI accelerator — are facing a compounding supply crunch driven by both volume demand and the physical challenge of supporting larger, more complex chip packages, per Tom's Hardware. ABF supply is heavily concentrated among a small number of Japanese suppliers — Ajinomoto itself, plus a limited set of substrate assemblers in Taiwan and South Korea — creating a chokepoint that sits several tiers below the chip fabs that typically receive strategic attention. As accelerator die sizes and multi-chiplet configurations expand, substrate area requirements grow non-linearly, and current capacity expansion timelines lag accelerator roadmaps.

Separately, China's Pacific Quartz has achieved qualification of its high-purity quartz for semiconductor equipment and DRAM manufacturing, reducing one specific import dependency, but the analysis from Tom's Hardware is explicit that Spruce Pine, North Carolina, retains a monopoly on the ultra-high-purity quartz used in silicon crucibles for crystal growth — the most demanding application. China's qualification covers equipment and DRAM production but not the crucible application that underpins leading-edge logic wafer production. This distinction matters: it is partial supply chain resilience, not full independence.

Broadcom's custom AI accelerator business is described as riding a rocketing growth trend, per Next Platform, reflecting the continuation of a strategy by Google, Meta, and Apple to develop application-specific silicon — XPUs, TPUs, and inference accelerators — that displace general-purpose NVIDIA GPUs for specific workloads. This is a confirmed revenue trend for Broadcom, whose networking and custom ASIC business is structurally tied to hyperscaler AI investment. The implication for NVIDIA is not near-term displacement at the frontier training tier, but meaningful erosion at the high-volume inference tier where cost per token is the primary metric.

d-Matrix's announcement that its Raptor memory-based XPU will be paired with NVIDIA rackscale infrastructure, reported by Next Platform, is a notable positioning move: rather than competing with NVIDIA at the system level, d-Matrix is inserting its inference-optimised hardware into NVIDIA's own rack architecture. This co-existence model — where alternative accelerators complement rather than replace NVIDIA iron — may prove more commercially durable than direct substitution attempts, and it reflects the reality that NVIDIA's networking and system software stack is itself a dependency that alternative silicon vendors must navigate.

Three separate analyses from Semiconductor Engineering converge on a common theme: the reliability and test frameworks developed for previous generations of data centre silicon are structurally inadequate for AI accelerators now operating at or above one kilowatt per chip. At these power densities, thermal behaviour under sustained workload diverges significantly from what automated test equipment captures at the component level, meaning chips that pass factory testing fail or degrade in field conditions. Silent data errors — bit-level corruptions that do not trigger system faults but introduce incorrect results into model outputs — are identified as a particularly insidious failure mode that is only now being systematically characterised across large fleets.

The operational implication is material: hyperscalers running large GPU clusters must now invest in continuous fleet monitoring, improved manufacturing screening protocols, and redesigned design-for-test architectures that can catch thermal and electrical margin failures that emerge only under production AI workloads. This is a cost and complexity burden that adds to total cost of ownership in ways that are not captured in per-GPU procurement pricing, and it disproportionately affects operators running dense, sustained inference workloads rather than bursty training jobs.