Compute & Infrastructure

OpenAI presented Jalapeño at Hot Chips 2026 as a 700W ASIC co-developed with Broadcom, claiming 1.9x throughput per kilowatt and 3.6x lower latency compared to Nvidia's GB300 NVL flagship, which draws 1,400W. Hardware VP Richard Ho framed it as delivering lower latency and higher throughput simultaneously — the two metrics that most directly govern inference economics. These are vendor-published benchmarks, not independent third-party results, and the specific workloads and configurations used for comparison have not been fully disclosed. The Verge, Tom's Hardware, ServeTheHome, and Data Center Dynamics all covered the announcement with broadly consistent technical details.

The Broadcom co-development relationship is strategically significant: it mirrors the Google TPU partnership model and confirms Broadcom's role as the primary custom ASIC partner for hyperscalers seeking to reduce Nvidia dependence. The power efficiency claim — halving TDP while outperforming on throughput — directly addresses the energy cost constraint that is becoming the binding limit on inference fleet economics. If the benchmarks hold under independent scrutiny, Jalapeño materially changes the build-versus-buy calculus for any hyperscaler currently committed to Nvidia inference clusters. OpenAI's stated intent to deploy Jalapeño at scale in its own infrastructure means the chip is not merely a research exercise.

Beyond Jalapeño, Hot Chips 2026 saw an unusually dense concentration of competing AI hardware disclosures. Google detailed its eighth-generation TPU family, splitting into TPU 8t for training and TPU 8i for inference — maintaining its status as the only hyperscaler with production training hardware independent of Nvidia. ServeTheHome noted the bifurcated approach signals different optimisation targets for the two workloads. Microsoft presented Maia 200, its second-generation inference processor, indicating continued commitment to custom silicon despite its deep Nvidia supply relationship. ServeTheHome Intel disclosed Crescent Island using the Xe3P architecture with HBM4 memory and liquid cooling, targeting AI FLOPS per watt for data centre inference. Tom's Hardware SambaNova presented its SN50 RDU, and Nvidia itself disclosed details of the Vera CPU and its integration of acquired Groq LPU technology for low-latency decode in heterogeneous Vera Rubin clusters.

Nvidia's Vera CPU disclosure is particularly notable: the 88-core chip with 1.2 TB/s SOCAMM2 memory bandwidth is being positioned for agentic workloads, and SpaceXAI has committed to deploying standalone Vera CPUs for Grok's agentic inference. Tom's Hardware The incorporation of Groq LPU technology for heterogeneous compute — specifically for the decode phase of inference — shows Nvidia using its acquisition to defend latency benchmarks against exactly the kind of claims OpenAI is making with Jalapeño. The simultaneous disclosure of competing architectures across Google, Microsoft, OpenAI, Intel, SambaNova, and Nvidia in a single conference week is a structural signal that the AI chip market is fragmenting along workload-specific lines.

China is deliberately slowing exports of germanium, quartz-based materials, and rare-earth magnets to Taiwan, according to Tom's Hardware. The framing as a strategic slowdown rather than an outright ban is significant: it applies maximum supply chain pressure while preserving deniability and avoiding a clean trigger for formal trade countermeasures. Germanium is critical for compound semiconductors and optical components; quartz-based materials are used in crucibles and wafer processing equipment; rare-earth magnets are foundational to robotics and precision manufacturing.

The targeting of Taiwan specifically — rather than a broader export restriction — indicates this is a calculated escalation in the semiconductor geopolitical competition rather than a generalised resource nationalisation move. TSMC, which fabricates the majority of advanced AI chips including Nvidia's GPUs and custom ASICs for Google and others, is headquartered in Taiwan. Any sustained restriction on these inputs threatens not just semiconductor production volumes but also the tooling and optical interconnect supply chains that underpin data centre networking. Inventory buffers and alternative sourcing from allied suppliers exist but are limited at scale. This development has not yet produced a confirmed production disruption, but the trend direction is unambiguous.

Micron Fellow Raghu Sreeramaneni used Hot Chips 2026 to deliver a notably direct warning: HBM already consumes approximately 3x more silicon per bit than DDR5, and this gap is widening with each successive generation. Tom's Hardware described the company's position as the memory wall being 'getting worse' as prices rise. This is a structural supply constraint, not a cyclical one. HBM production requires significant wafer area, advanced 3D stacking, and yields that remain challenging relative to planar DRAM. The three primary HBM suppliers — SK Hynix, Samsung, and Micron — are all capacity-constrained, and SK Hynix has publicly stated it is sold out of HBM through 2025 and into 2026.

Samsung's simultaneous disclosure at Hot Chips of LPDDR5X-PIM — processing-in-memory DRAM achieving 3.01x faster AI inference throughput and 8x bandwidth versus standard LPDDR5X — is directionally relevant here. Tom's Hardware PIM architectures could partially mitigate the HBM supply pressure for inference at the edge and in less memory-bandwidth-intensive deployments, reducing demand on the scarce HBM wafer pool. However, for the large-scale training and high-throughput inference deployments that dominate hyperscaler demand, HBM remains irreplaceable in the near term.

Three concurrent developments illustrate the acute power constraint facing AI data centre buildout. Nano Nuclear has announced a non-binding partnership with Tillman Digital targeting up to 6GW of micro-reactor nuclear capacity at US data centres by 2040 — a figure that remains speculative given the regulatory and deployment timeline for small modular reactors. Data Center Dynamics The 2040 horizon and non-binding status of the deal should be read as an intention signal rather than confirmed capacity. Meanwhile, Cummins VP Stiven Smith articulated natural gas as the practical near-term bridge for grid-constrained AI data centre deployments, reflecting an industry-wide acknowledgement that grid connection timelines — often 4-7 years for large interconnections in the US — are a binding constraint on expansion plans. Data Center Dynamics

Nvidia's investment in Lancium — a company that controls large-scale, power-ready land sites — is a more immediately actionable development. By taking a direct stake, Nvidia is ensuring its customers have access to pre-permitted, grid-connected capacity, effectively moving upstream in the data centre value chain to remove a key bottleneck. Data Center Dynamics Community opposition to a proposed 50MW conversion of a Bitcoin mining facility to AI/HPC in Hopkinsville, Kentucky illustrates the local permitting risk that applies even to sites with existing power infrastructure. Data Center Dynamics Separately, Nebius closed $5.75bn in senior notes to expand its data centre and GPU fleet Data Center Dynamics, and Starcloud raised $250m at a $2.3bn valuation for orbital data centres — a speculative but increasingly funded alternative compute geography that bypasses terrestrial power and land constraints entirely. Data Center Dynamics