Compute & Infrastructure

OpenAI and Broadcom have revealed Jalapeño, described as a 'blank-slate design for modern LLM inference, not a general-purpose accelerator adapted from earlier AI workloads.' The chip is a reticle-sized ASIC — meaning it occupies the maximum die area a lithography machine can expose in a single pass — and was developed in an unusually compressed nine-month cycle. According to Tom's Hardware, the chip reportedly beats leading-edge alternatives on performance-per-watt for inference workloads.

The Broadcom partnership is strategically significant. Broadcom has become the dominant custom ASIC partner for hyperscalers — it already designs TPUs for Google — and OpenAI's move follows the same playbook: use Broadcom's packaging and networking expertise to build silicon optimised for a specific workload rather than paying NVIDIA's margin premium for general-purpose GPUs. Data Center Dynamics notes the chip is positioned for both current and future LLMs, suggesting OpenAI intends Jalapeño as a platform, not a one-off. The nine-month development timeline, if accurate, signals that AI-era ASIC iteration cycles are compressing dramatically.

Two developments this week confirmed that high-bandwidth memory is the critical and capacity-constrained input to AI infrastructure. Micron guided to $50 billion in Q4 revenue, crushing estimates, with analysts at Wedbush citing pricing power driven by AI-fuelled component shortages, per Bloomberg. Simultaneously, SK Hynix filed for a Nasdaq listing targeting up to 45.45 trillion won ($29.4 billion), with all proceeds explicitly directed to advanced AI memory fabrication capacity and EUV tool orders, per Tom's Hardware.

Kioxia separately announced plans for US depositary shares in spring 2027, per Bloomberg, further signalling that the memory sector is tapping public equity markets aggressively to fund the capex required to stay relevant in HBM supply chains. The pattern is clear: memory makers face a multi-year capacity deficit in HBM3E and the emerging HBM4 generation, and are racing to lock in EUV tool allocations — themselves constrained by ASML's production schedule — before competitors do. The pricing power Micron demonstrated is not cyclical; it reflects genuine structural undersupply against AI training and inference cluster demand.

TSMC has reportedly notified customers of 5–10% wafer price increases across all advanced nodes, extending from leading-edge 3nm down through 7nm and into some legacy processes — a scope covering 74% of the company's wafer business, per Tom's Hardware. This is unconfirmed by TSMC publicly, but the report aligns with TSMC's pattern of annual pricing negotiations and the company's stated intention to improve margins to fund its US and Japan fab expansions.

The strategic implication is asymmetric. Customers with the highest wafer volumes — NVIDIA, Apple, AMD, Qualcomm — have more negotiating leverage but cannot easily absorb percentage-point margin compression at scale. More critically, the price increase affects the economics of the custom ASIC movement: if TSMC advanced node pricing rises, the cost advantage of purpose-built inference chips over NVIDIA GPUs narrows, since ASICs and GPUs largely compete on the same advanced nodes. The hikes also raise the floor cost for sovereign AI compute programmes attempting to onshore chip production — higher TSMC wafer prices make the economics of domestic alternatives marginally more attractive.

China's LineShine supercomputer has claimed the top position on the 67th TOP500 list with 2.198 exaflops, achieved using a CPU-only architecture with no GPU accelerators, per Tom's Hardware. This is a direct technological response to US export controls that have denied China access to NVIDIA's H100 and A100 at scale. The achievement demonstrates that Chinese domestic processor development — likely based on domestic CPU designs — has reached the point where extreme parallelism can substitute for GPU acceleration in benchmarkable HPC workloads, though the architecture's efficiency for AI training specifically remains an open question.

The parallel data point is the black market: NVIDIA A100 servers that are five years old and commercially obsolete in Western markets are now fetching up to $82,000 in China following a smuggling crackdown and customs freeze, per Tom's Hardware. The tripling of A100 prices signals acute GPU scarcity in the Chinese AI ecosystem and validates that export controls are biting. Together, these two data points frame China's infrastructure strategy: pursue domestic CPU-based HPC in parallel with aggressive grey-market GPU acquisition, while Huawei's Ascend accelerator programme attempts to provide a third path.

Qualcomm used its 2026 Investor Day to project over $15 billion in annual data center chip sales by fiscal 2029, with billions in revenue already expected in fiscal 2027 following the addition of Meta as a customer, per Bloomberg and ServeTheHome. The product lineup includes the Dragonfly C1000 CPU, AI accelerators, and a high-bandwidth compute interconnect positioned as an HBM alternative. These are announced projections, not confirmed revenue — but Meta's validation as a customer provides meaningful credibility that Qualcomm's data center silicon is past the prototype stage.

Against this hardware investment surge, Tom's Hardware reports that data center construction faces a critical skilled labour shortage that could slow deployment timelines despite available capital. Electrical engineers, specialised data centre technicians, and high-voltage infrastructure workers are in short supply relative to the concurrent global buildout across the US, Europe, and the Gulf. This is a non-financial constraint that capital allocation cannot immediately solve — training pipelines for specialised trades operate on multi-year timescales.