Compute & Infrastructure

Through-silicon vias — the vertical electrical connections that enable high-bandwidth memory stacking and advanced chiplet integration — are now identified as a manufacturing chokepoint in their own right, according to analysis from Semiconductor Engineering. TSV formation requires extreme precision in etching, deposition, and planarization across wafers that are increasingly thinned to sub-50 micron thicknesses, and yield losses at this step propagate through the entire package. The constraint is not simply capital investment — it is process maturity at scale.

This matters structurally because HBM2e, HBM3, and HBM3e — the memory architectures attached to NVIDIA H100, H200, and Blackwell GPUs, as well as AMD MI300X — all depend on TSV interconnects. SK Hynix, Samsung, and Micron are the only suppliers with volume TSV capability. Any yield or throughput degradation at the TSV step directly constrains how many AI accelerators can ship at full memory bandwidth specification. The bottleneck sits upstream of the final assembly houses (primarily TSMC's CoWoS and Samsung's I-Cube lines) and is therefore not resolved by simply adding more packaging capacity.

Reports confirmed this week that Intel is cancelling all discrete gaming GPUs under its Xe3P Arc 'Celestial' architecture, with even the follow-on Xe4 'Druid' generation in 2027 unconfirmed for consumer discrete parts, according to Tom's Hardware. Intel is reallocating its graphics IP investment to data centre accelerators and workstation GPUs, and integrating the architecture into mobile SoCs.

The strategic read is straightforward: Intel is acknowledging it cannot sustain a credible three-front GPU war across gaming, data centre, and mobile simultaneously, and is choosing the segment where AI spend is concentrated. However, Intel's data centre GPU position remains weak relative to NVIDIA and AMD — its Gaudi 3 accelerator has seen limited hyperscaler adoption. Exiting consumer discrete GPUs does not automatically translate into data centre GPU competitiveness; it primarily signals resource reallocation rather than confirmed traction. The net effect for the AI compute market is a further reduction in the number of credible GPU competitors, entrenching NVIDIA's pricing power in training and inference hardware.

Gartner raised its global IT spending growth forecast by nearly three percentage points in the same week the IEA characterised the ongoing US/Israel/Iran conflict as producing the worst energy crisis the world has faced, according to The Register. The growth is attributed specifically to cloud and AI infrastructure investment. This decoupling is analytically significant: historically, energy price shocks with this magnitude have suppressed capex-intensive infrastructure buildout. The current cycle appears to be inverting that relationship, with AI infrastructure treated by hyperscalers and enterprises as non-discretionary strategic spending.

The risk embedded in this dynamic is that energy cost escalation does not disappear — it defers or concentrates. Data centre operators are signing long-term power purchase agreements and investing in on-site generation precisely because grid power is increasingly unreliable and expensive in conflict-proximate regions. The divergence between IT spending momentum and energy reality will eventually close, either through energy constraint forcing capacity rescheduling, or through sustained productivity gains from AI justifying the energy cost premium. Neither outcome is certain at this stage.

Investor flows into Chinese optical component stocks are accelerating on the thesis that AI-driven demand for transceiver and interconnect hardware will outpace Western suppliers' capacity, according to Bloomberg. Separately, AI chip startup Blaize and hardware developer NeoTensr announced a partnership to build edge AI infrastructure for the Asia-Pacific region, targeting smart cities, logistics, and automation, per Data Centre Dynamics.

These two developments are directionally related: they indicate that the AI infrastructure supply chain is bifurcating at the component and system level, with Asian-market players building differentiated supply chains for optical interconnects and edge compute rather than relying on the Western-dominated hyperscaler stack. Chinese optical suppliers — including Innolight, Eoptolink, and HG Genuine — already hold significant share in 400G and 800G transceivers used in data centres globally. If AI-driven demand accelerates further, their role in the infrastructure supply chain grows regardless of export control regimes targeting compute chips.

NextPlatform published analysis arguing that GPU-hours is an increasingly inadequate unit for measuring AI training costs, as architectural heterogeneity — across TPUs, custom ASICs, and disaggregated memory-compute configurations — makes cross-system cost comparisons using a GPU-hour baseline structurally misleading, per NextPlatform. The argument is that total cost of ownership metrics need to account for memory bandwidth utilisation, interconnect efficiency, and power draw per useful training FLOP rather than raw accelerator-hours.

This is a methodological issue with direct procurement implications. Infrastructure buyers who are benchmarking cluster buildout decisions using GPU-hour cost comparisons may be systematically underweighting the advantage of purpose-built architectures (Google TPU v5, AWS Trainium 2, Cerebras WSE) in specific training regimes. As the hyperscalers move a larger share of their internal training workloads onto custom silicon, the GPU-hour benchmark increasingly reflects only the open-market inference and third-party training cost surface, not the frontier.