Compute & Infrastructure

Meta will fund construction of seven new natural gas power plants through a partnership with utility Entergy to supply its Louisiana data centre with 7 gigawatts of capacity, according to Tom's Hardware. This represents the most significant fossil fuel infrastructure investment yet disclosed by a hyperscaler for AI compute, dwarfing prior arrangements that typically involved power purchase agreements rather than direct funding of generation capacity. The move indicates that despite public commitments to renewable energy, the timeline and scale requirements of AI data centre expansion cannot be met by nuclear or renewable sources in the near term.

The commitment arrives as tech giants' aggregate capital spending is projected to reach $700 billion driven by AI demand, according to a Data Center Dynamics sponsored analysis. Political resistance is mounting simultaneously — Senator Bernie Sanders and Representative Alexandria Ocasio-Cortez are introducing legislation for a moratorium on new AI data centres, citing impact on energy prices, as reported by Bloomberg. Representative Suhas Subramanyam from Virginia, home to the largest US data centre concentration, argued instead for geographic distribution of buildout rather than complete halt.

Four Chinese universities including two conducting military research for the PLA acquired Supermicro servers equipped with Nvidia A100 AI chips in 2025 and 2026 despite US export restrictions, according to public procurement documents reviewed by Tom's Hardware. The A100 has been subject to export licensing requirements for China since October 2022, with further restrictions tightened in October 2023. The documented purchases indicate either violations by intermediaries in the distribution chain or exploitation of exemptions intended for civilian research institutions.

This enforcement failure undermines the strategic premise of US semiconductor export controls — that restricting access to advanced AI accelerators can slow Chinese military AI development. The breach occurred through commercial server vendors rather than direct chip sales, suggesting that controls focused on semiconductor manufacturers may miss vulnerabilities in the systems integration and distribution layers where entity verification is weaker.

A farming family in Northern Kentucky rejected a $26 million offer for 600 acres from an unnamed AI data centre developer despite the price exceeding local market rates by more than seven times, according to Tom's Hardware. The family cited agricultural production priorities and unwillingness to sell despite financial incentive. While anecdotal, the incident reflects growing friction between hyperscaler land acquisition strategies and local communities, occurring alongside federal legislative pushback. The willingness of developers to offer multiples above market rate indicates land availability is becoming a binding constraint in preferred locations near existing power infrastructure and fibre connectivity.

SRAM has failed to scale effectively at recent advanced process nodes, creating a widening gap between compute capability and memory access speed that affects all computing architectures according to Semiconductor Engineering analysis. The technical challenge stems from leakage current and voltage variability that worsen at smaller geometries, making SRAM cells unreliable below certain dimensions even as logic transistors continue shrinking. This mismatch forces chip designers to trade off cache size against die area and power consumption, limiting the performance improvements available from node transitions. No viable SRAM replacement technology has emerged at commercial scale — alternatives such as MRAM and ReRAM face their own density, speed, or endurance limitations that prevent drop-in substitution.

The memory wall directly impacts AI accelerator performance, where massive parameter sets and activation values must move between compute units and memory hierarchies. Current approaches involve increasingly complex on-chip network designs to optimise data movement, as detailed in a separate Semiconductor Engineering piece on NoCs and fabrics, but these are palliative measures rather than solutions to the underlying SRAM constraint.