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Compute & Infrastructure

19 sources analyzed to give you today's brief

Top Line

Chinese chipmaker CXMT doubled revenue to $8 billion in 2025 ahead of a major IPO, signalling Beijing's progress in building domestic memory capacity that could challenge South Korean and US dominance in HBM supply for AI workloads.

Data centre infrastructure supply chains are hitting critical bottlenecks beyond chips — Panasonic reports backup batteries sold out years in advance, while Micron's Singapore fab expansion requires 400-500 power transformers, more than double typical demand and exceeding any single manufacturer's annual output.

PC manufacturers face CPU lead times stretching to six months, up from two weeks, as Intel and AMD struggle to meet AI-driven demand, exposing capacity constraints even in mature semiconductor nodes.

Super Micro co-founder arrested for smuggling AI accelerators to China worth billions demonstrates how export controls are reshaping global supply chains and creating underground markets for advanced compute.

Key Developments

Chinese Memory Maker CXMT Emerges as Strategic HBM Competitor

ChangXin Memory Technologies Inc. more than doubled revenue to $8 billion in 2025, positioning the state-backed Chinese chipmaker as a credible challenger in high-bandwidth memory supply ahead of a domestic IPO, according to Bloomberg. The company's growth comes as Beijing prioritises semiconductor self-sufficiency and AI infrastructure buildout, with HBM representing a critical chokepoint given SK Hynix, Samsung, and Micron's near-monopoly on supply for Nvidia's H100 and subsequent generations. CXMT's trajectory mirrors China's broader strategy to build parallel supply chains insulated from US export restrictions.

Why it matters

A viable domestic HBM supplier would reduce China's dependency on Western-controlled memory supply and could eventually enable indigenous AI chip designs to achieve competitive performance, fundamentally altering the semiconductor geopolitical landscape.

What to watch

CXMT's ability to scale production and match the technical specifications required for cutting-edge AI accelerators, particularly thermal performance and bandwidth density that SK Hynix currently leads.

Data Centre Electrical Infrastructure Becomes the New Bottleneck

Micron's planned $24 billion NAND flash expansion in Singapore will require 400-500 power transformers, more than double the 100-150 units a standard fab typically needs and exceeding the annual production capacity of any single transformer manufacturer, according to Tom's Hardware. Separately, Panasonic reports data centre backup batteries are sold out years in advance as hyperscalers lock in supply, according to The Register. The company is shifting production from automotive to compute applications and developing supercapacitors as an alternative protection mechanism. Bloomberg reports Prologis CEO Dan Letter confirmed the logistics firm is securing longer-term power capacity commitments with hyperscalers, indicating infrastructure players are extending procurement timelines to match multi-year buildout cycles.

Why it matters

Heavy electrical infrastructure—transformers, switchgear, battery systems—operates on multi-year procurement cycles and cannot be scaled as rapidly as server hardware, creating a physical ceiling on data centre expansion regardless of chip availability.

What to watch

Whether governments fast-track electrical equipment manufacturing capacity or streamline grid interconnection approvals to prevent power infrastructure from becoming the binding constraint on AI compute buildout through 2027-2028.

CPU Supply Tightens as AI Workloads Drive Unexpected Demand

PC manufacturers report lead times for Intel and AMD CPUs have stretched to six months, up from the typical two weeks, as AI demand creates unexpected pressure on mature process nodes, according to Tom's Hardware. The shortage suggests AI PC features and edge inference workloads are driving volume beyond industry forecasts, straining foundry capacity allocation. Intel's release of Xeon 600 workstation chips and new vPro Panther Lake CPUs with integrated AI capabilities, as reported by Tom's Hardware, indicates both chipmakers are pivoting mainstream product lines toward AI-optimised architectures, potentially exacerbating capacity constraints as fabs retool.

Why it matters

The CPU shortage demonstrates that AI infrastructure demand extends beyond data centre GPUs to encompass the entire compute stack, including client devices and edge systems, creating cascading capacity constraints across semiconductor manufacturing.

What to watch

Whether Intel and AMD can rebalance foundry allocations or if extended lead times persist through 2026, potentially forcing OEMs to redesign products around available processors rather than optimal specifications.

Export Control Evasion Creates Underground AI Accelerator Market

A co-founder of Super Micro Computer has been arrested and charged with smuggling AI chips to China in deals worth several billion dollars, with multiple managers and contractors implicated and one suspect remaining a fugitive, according to Tom's Hardware. The case reveals sophisticated evasion networks exploiting gaps in supply chain oversight as US restrictions on advanced AI chips to China tighten. The arrest demonstrates enforcement is intensifying, but the scale of the alleged operation suggests significant compute has already reached restricted destinations through gray-market channels.

Why it matters

Export controls only function if enforcement matches policy ambition—widespread evasion would enable China to access cutting-edge AI compute despite restrictions, undermining the strategic rationale for semiconductor sanctions while fragmenting global supply chains.

What to watch

Whether US authorities can establish effective end-use verification systems or if the incentive differential between restricted and unrestricted markets creates persistent smuggling economics that outpace enforcement.

Signals & Trends

Software Optimisation Becomes Infrastructure Efficiency Lever as Hardware Constraints Bite

Google's TurboQuant compression technique reduces AI model cache memory requirements by six times and delivers up to 8x performance increases on Nvidia H100 GPUs by compressing key-value caches to 3 bits with no accuracy loss, according to Tom's Hardware. As memory and power become binding constraints, algorithmic improvements that reduce infrastructure demands per unit of inference are gaining strategic importance alongside raw buildout. This suggests the next phase of AI infrastructure competition will reward organisations that optimise the full stack—silicon, systems, and software—rather than simply scaling hardware.

Sovereign AI Compute Buildout Accelerates in Mid-Tier Economies

Poland's Ministry of Digital Affairs funded an $8.1 million Nvidia-powered AI supercomputer at the NASK research institute for government and enterprise use, while Ericsson secured access to Europe's fastest supercomputer, Jupiter, to train large-scale AI models for 6G development, according to Data Center Dynamics and Data Center Dynamics. These investments indicate mid-tier economies are prioritising domestic AI compute capacity to avoid dependency on US and Chinese cloud infrastructure, creating a fragmented landscape where strategic workloads increasingly run on nationally controlled hardware.

Power Delivery and Thermal Management Emerge as Packaging-Level Constraints

Semiconductor Engineering reports thermal management is now the biggest performance and reliability bottleneck in multi-die assemblies, with 3D packaging creating heat dissipation challenges that limit clock speeds and system density, according to Semiconductor Engineering. Separately, AI chip startup Epic Microsystems raised $21 million specifically for power delivery system development, according to Data Center Dynamics. These developments suggest the industry is hitting fundamental physics constraints where chiplet architectures and advanced nodes require rethinking power distribution and cooling at the package level, not just the die or system level—potentially slowing the pace at which new process nodes translate into deployable performance gains.

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